
// Library name: DOMINO
// Cell name: SINGLE_VTL_AND_SLEEP
// View name: schematic
V0 (vdd! 0) vsource dc=1.1 type=dc
M4 (OUT net24 0 0) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 ps=300n \
        pd=300n ld=105n ls=105n m=1
M3 (net24 SLEEP 0 0) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 ps=300n \
        pd=300n ld=105n ls=105n m=1
M2 (net24 A net28 0) NMOS_VTL w=270.0n l=50n as=2.835e-14 ad=2.835e-14 \
        ps=480.0n pd=480.0n ld=105n ls=105n m=1
M1 (net28 B net32 0) NMOS_VTL w=270.0n l=50n as=2.835e-14 ad=2.835e-14 \
        ps=480.0n pd=480.0n ld=105n ls=105n m=1
M0 (net32 CLK 0 0) NMOS_VTL w=270.0n l=50n as=2.835e-14 ad=2.835e-14 \
        ps=480.0n pd=480.0n ld=105n ls=105n m=1
M7 (OUT net24 vdd! vdd!) PMOS_VTL w=180.0n l=50n as=1.89e-14 ad=1.89e-14 \
        ps=390.0n pd=390.0n ld=105n ls=105n m=1
M6 (net24 CLK vdd! vdd!) PMOS_VTL w=180.0n l=50n as=1.89e-14 ad=1.89e-14 \
        ps=390.0n pd=390.0n ld=105n ls=105n m=1
M5 (net24 OUT vdd! vdd!) PMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
